9–13 Sept 2024
Wanda Realm Beijing
Asia/Shanghai timezone
Paper Submission Deadline: September 5 (23:59 UTC+8), 2024

The development of new BPM signal processor at SSRF

TUP27
10 Sept 2024, 16:00
1h 30m
China Hall 3

China Hall 3

Poster Presentation MC3: Beam Position Monitors TUP: Tuesday Poster Session

Speaker

Mingjie Zhang

Description

A BPM signal processor has been developed for SSRF since 2009. It composed of Virtex5 FPGA, ARM board, and 4 125MSPS sampling rate ADCs. Since then, electronic technology has made significant progress. Such as Zynq UltraScale+ MPSoC FPGA contains both hard-core ARM and high-performance FPGA, and ADCs with a sampling rate of 1GSPS have been applied in mass production. A new BPM processor with Zynq UltraScale+ MPSoC FPGA and 1GSPS ADCs is under development at SSRF. Due to the application of new technologies, the processor performance will be significantly improved. The new processor can also meet the needs of ultra-low emittance measurement for the new generation of light sources. This paper will introduce the design of the processor and the relative tests.

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Primary author

Co-authors

Longwei Lai (Shanghai Advanced Research Institute) Yimei Zhou (Shanghai Advanced Research Institute) Yingbing Yan ((Shanghai Advanced Research Institute))

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