Speaker
Description
This paper presents the design of a parameter-tunable turn-by-turn feedback system, integrating front-end analog and digital signal processing modules onto a single functional board. Tailored for storage rings such as BEPCII and HEPS, the system is capable of filtering the revolution frequency and adjusting the feedback phase within 0.5 ms to generate correction signals. Building upon existing self-developed feedback electronics and the IHEP digital BPM system, this study investigates signal down-conversion, sampling theory, clock phase-locked loops (PLL), and high-speed circuit design. We selected optimal ADC and DAC chips based on BEPCII parameters and designed a custom Analog Front-End (AFE) board to acquire down-converted sampling data. Furthermore, various Finite Impulse Response (FIR) filters were modeled in MATLAB. By comparing the frequency responses of filters designed via the Least Squares method and the Window method, optimal coefficients were determined and implemented in the FPGA. Crucially, the system addresses the phase relationship between the pickup and the kicker. Since the feedback signal requires a specific phase shift relative to the BPM signal (nominally 90°) plus the beam transit phase, the design incorporates a tunable coefficient mechanism. This allows for precise adjustment of the filter's phase-frequency response to ensure the correct feedback phase is achieved.
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| Supervisor's name | yue junhui |
| Supervisor's email | yuejh@ihep.ac.cn |
| Paper submission software | LATeX |