IPAC'23 - 14th International Particle Accelerator Conference

Design study of 972-MHz RF and clock generator board at J-PARC linac

THPA101

11 May 2023, 16:30

2h

Salone Adriatico

Poster Presentation MC6.T27: Low Level RF Thursday Poster Session

Speaker

Kenta Futatsukawa (High Energy Accelerator Research Organization)

Description

In the J-PARC linac, the low-level RF (LLRF) with the digital feedback (DFB) and the digital feedforwaed (DFF) of the cPCI system had been adopted to satisfy the requirement of amplitude and phase stabilities. It has been operated without a serious problem so far. However, more than 15 years have passed since the construction of the J-PARC linac and the life of the apparatuses used since the time of construction is approaching. Some apparatuses are now discontinued and cannot be purchased, and others have problems such as software development environments that only use on older OSs. Therefore, we are starting to develop the next generation LLRF system. Currently, the 324-MHz LLRF stations, approximately half of all systems, are replaced by new DFB and DFF system based on MTCA.4. As a next step, we will develop new 972-MHz DFB and DFF system. The analog boards cannot be shared with the 324-MHz DFB and DFF system due to the different frequencies. The digital board will be re-examined to reduce the latency. In this paper, we would like to introduce the plan to replace the DFB and DFF systems at J-PARC Linac and show the design study of the RF and clock generator board.