17–22 May 2026
C.I.D
Europe/Zurich timezone

Design and Testing of a Universal Embedded Feedback Controller for RF Cavities

MOP6698
18 May 2026, 16:00
2h
C.I.D

C.I.D

Deauville, France
Poster Presentation MC6.T27: Instrumentation: Low Level RF Poster session

Speaker

Mr Ashish Sharma (Indian Institute of Technology Delhi)

Description

The design of low-level feedback (LLRF) controllers used to stabilize the amplitude and phase of the field inside the RF cavities is typically customized, depending on the frequency and mode of operation. IUAC, New Delhi, India, operates accelerators with RF structures in the range of 12.125-97 MHz, in both normal and superconducting modes. Currently, all the LLRF controllers that have been operational for many years are structure-specific and designed in the analog electronics domain. Component ageing, obsolescence, and limited availability have made it challenging to maintain them due to frequent failures. To overcome this, a universal digital controller has been developed whose design is based on the philosophy of using the same hardware for all the RF structures at IUAC. It is a compact, reconfigurable, and standalone device featuring a microcontroller programmed fractional Phase Locked Loop multiplier for generating various LO signals and system clocks, a wideband analog front end for up/down conversion and signal conditioning, and a System-on-Chip FPGA-based digital board with fast ADCs and DACs, all controlled using an EPICS IOC. The controller is designed as a Sawtooth Waveform Generator for the multi-harmonic buncher, a generator-driven, and a self-excited loop-based LLRF for various RF cavities at IUAC. It operates within acceptable limits of 1% RMS variation in amplitude & a ±1-degree variation in phase. Design details & test results will be discussed in the paper.

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Authors

Mr Ashish Sharma (Indian Institute of Technology Delhi) Bhuban Kumar Sahu (Inter-University Accelerator Centre) Mr Paramanand Singh (Indian Institute of Technology Delhi, Inter-University Accelerator Centre) Mr S. Venkatramanan (Inter-University Accelerator Centre) Prof. Subrat Kar (Indian Institute of Technology Delhi) Mr V.V.V. Satyanarayana (Inter-University Accelerator Centre) Mr Yaduvansh Mathur (Inter-University Accelerator Centre) Mr Yatesh Dabas (Inter-University Accelerator Centre)

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