Speaker
Description
Maintaining a constant phase difference between the reference (Ref) and cavity voltage sampling (Pt) signals is critical for stable operation of the Hefei Light Source (HLS) storage ring's RF system. This requires high-precision real-time phase detection capable of identifying lead or lag, to quickly restore the preset phase after startup or recovery, and to maintain the relationship between the beam synchronous phase in the low-level RF (LLRF) loop and the bunch-by-bunch feedback system. Conventional phase detection methods, based on either phase detector chips or the CORDIC algorithm, face inherent drawbacks. The former has limited accuracy (> ±2°) and needs extra circuitry to determine phase lead/lag, increasing design complexity. The latter requires a high-speed data acquisition system and dedicated processing algorithms, significantly increasing system complexity and cost. To overcome these limitations, this paper proposes a novel phase detection scheme using a Time-to-Digital Converter (TDC) implemented in a Field-Programmable Gate Array (FPGA). The design employs multi-phase TDC and averaging techniques, enabling fast and accurate measurements immune to transmission line delays. The system achieves a phase resolution of 0.359°, requires only one-time calibration, and reliably meets long-term online phase detection needs for the HLS.
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