Speaker
Description
The power upgrade of the China Spallation Neutron Source Phase II (CSNS-II) requires the Rapid Cycling Synchrotron (RCS) BPM system to operate under an extreme 107 dB ultra-wide dynamic range (20 mV to 50 V) and high signal power. The primary design challenges are mitigating thermal drift, suppressing reflections from impedance mismatch, and enhancing low-energy SNR.This paper presents the preliminary design and performance validation of an analog front-end board, adapting successful solutions from facilities like J-PARC MR. The design integrates thin-film resistor attenuators with an impedance tuning network for improved stability and reflection control. Crucially, a hybrid fast/slow switching attenuation strategy is applied: millisecond-level slow switching handles macroscopic changes, while innovative nanosecond-level fast switching enables dynamic gain conditioning during acceleration, significantly boosting the system's SNR.Performance verification results (including attenuation and S21 characteristics) confirm the feasibility and core metrics of the circuit under high-power conditions, providing essential technical guidance for the final implementation at the CSNS-II RCS.
| In which format do you inted to submit your paper? | Word |
|---|