An FPGA-based autoencoder model for real-time RF signal denoising for industrial accelerators

WEPD024
24 Sept 2025, 16:30
1h 30m
Palmer House Hilton Chicago

Palmer House Hilton Chicago

17 East Monroe Street Chicago, IL 60603, United States of America
Poster Presentation MC05: FPGA and Embedded Systems WEPD Posters

Speaker

Vikshar Rajesh (RadiaSoft (United States))

Description

A challenge that industrial particle accelerators face is the high amounts of noise in sensor readings. This noise obscures essential beam diagnostic and operational data, limiting the amount of information that is relayed to machine operators and beam instrumentation engineers. Machine learning-based techniques have shown great promise in isolating noise patterns while preserving high-fidelity signals, enabling more accurate diagnostics and performance tuning. Our work focuses on the implementation of a real-time FPGA-based noise reduction autoencoder, tested on a Xilinx ZCU104 evaluation kit with the intention of being deployed on industrial particle accelerators in the near future.

Funding Agency

Department of Energy, Office of Science, Office of Accelerator R&D and Production.

Author

Vikshar Rajesh (RadiaSoft (United States))

Co-authors

Jonathan Edelen (RadiaSoft (United States)) Joshua Einstein-Curtis (RadiaSoft (United States))

Presentation materials

There are no materials yet.