Development status of FPGA-based FOFB system for PLS-II

WEPD023
24 Sept 2025, 16:30
1h 30m
Palmer House Hilton Chicago

Palmer House Hilton Chicago

17 East Monroe Street Chicago, IL 60603, United States of America
Poster Presentation MC05: FPGA and Embedded Systems WEPD Posters

Speaker

Wooseong Cho (Pohang Accelerator Laboratory)

Description

The third-generation synchrotron accelerator Pohang Light Source-II (PLS-II) at Pohang Accelerator Laboratory uses a Fast Orbit Feedback (FOFB) system to maintain beam orbit stability in the storage ring. The FOFB system operates in real time to suppress orbit perturbations in both horizontal and vertical directions. Currently, the system uses VME-based Single Board Computers (SBCs) and Reflective Memory (RFM) technology, achieving a feedback repetition rate of about 1kHz. However, the aging hardware is causing difficulties in maintenance and performance upgrades. To solve this issue, a new FOFB system based on Zynq UltraScale+ FPGA high-speed digital processing technology is under development, aiming to increase the feedback rate to 10 kHz. The new design distributes twelve independent FOFB controllers throughout the storage ring to minimize latency from Beam Position Monitor (BPM) Fast Acquisition (FA) data reception to the output of control signals to the magnet power supplies. The system is being developed to work stably with the existing Fast Magnet Power Supplies at 1 kHz and also to support future high-performance supplies capable of operating at higher rates. The FPGA-based FOFB system is currently under development, with a goal of achieving a control bandwidth greater than 100 Hz and significantly improving maintainability and scalability. This paper introduces the design concept and the current development status of the new system.

Author

Wooseong Cho (Pohang Accelerator Laboratory)

Co-authors

Jaeyu Lee (Pohang Accelerator Laboratory) Ilmoon Hwang (Pohang Accelerator Laboratory) Changbum Kim (Pohang Accelerator Laboratory)

Presentation materials

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