ICALEPCS 2025 - The 20th International Conference on Accelerator and Large Experimental Physics Control Systems

Readout of the FPGA-based global trigger system of the ATLAS experiment

MODR001

22 Sept 2025, 16:00

15m

Red Lacquer Room (Palmer House Hilton Chicago)

Contributed Oral Presentation MC05: FPGA and Embedded Systems MODR MC05 FPGA and Embedded Systems

Speaker

Mr Tong Xu (Argonne National Laboratory)

Description

A new FPGA-based Global Trigger system is intended for the Phase-II Upgrade of the ATLAS experiment at the High-Luminosity Large Hadron Collider (HL-LHC). The system will process data from the experiment with fixed latency to allow the selection of individual collisions of proton bunches with physical potential. Intermediate data from the Global Trigger system are read out for the collisions of interest for trigger decision verification with commodity computing. The readout of the Global Trigger is handled by the readout firmware, which interfaces with the ATLAS readout system. The firmware receives trigger decisions, timing and control signals via the 9.6 Gb/s ATLAS Local Trigger Interface (LTI) link and outputs data via the 25 Gb/s Interlaken link. A prototype of this readout firmware has been designed and tested on the Global Common Module (GCM) boards equipped with AMD Versal Premium FPGAs.