Speaker
Description
The Taiwan Photon Source's (TPS) Front-End Interlock System has been upgraded to solve operational complexity and maintainability that were noticed in the early stages of operation. For increased dependability and fault-handling capabilities, one of the main enhancements is switching the logic core from an FPGA-based architecture to a fault-tolerant dual-sequential CPU architecture.
The system integrates redundant dual CPUs with shared relay monitoring and adopts a Real-Time Operating System (RTOS) to optimize signal processing. Additionally, the safety functionalities have been restructured to include fail-safe mechanisms, independent loop monitoring, and improved logic for cooling water flow and vacuum monitoring. These updates aim to reduce unnecessary emergency shutdowns and improve system reliability.
While preserving compatibility with the legacy system, this new version streamlines the design, increases diagnostic efficiency, and expedites the deployment process for future upgrades.
| Region represented | Asia |
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